The present invention relates to a clock signal producing circuit for a data storing and reproducing system, and more particularly to a clock signal producing circuit for producing a clock signal for a data storing and reproducing system according to a sampled format method.
A DRAW (Direct Read After Write) optical disk for example, stores servo bytes as shown in FIG. 3. Each sector of the optical disk is formed of forty-three servo blocks, each block having a servo byte of two bytes followed by a data-byte of 16 bytes. The servo byte includes two wobbled pits and one clock pit. The wobbled pits are disposed on both sides of a track center. When the information-detecting point of a pickup (light spot for detecting information) moves onto the track center, the decreases in the amount of light reaching the wobbled pits on bothsides become equal. When the information-detecting point of the pickup is displaced laterally, the decreases in amount of light reaching the two wobbled pits vary in accordance with the direction and amount of the displacement. Therefore, a tracking error signal is produced based on the difference (difference in an RF signal level) between the decrease in the amount of light at the two locations. This tracking error signal is maintained during a subsequent data byte section. In addition, the two wobbled pits alternately form a long section and a short section every 16 tracks. By detecting alternation of these long and short sections, it is possible to count the number of tracks even when searching at high speed (16 track counting). Further, a distance D between the wobbled pit and the subsequently located clock pit is set to a predetermined length, which does not appear in the data bytes. Thus the distance D can be detected as a synchronous signal. Various timing signals are produced on the basis of this detected synchronous signal. The clock signal is produced in accordance with the detection of the clock pit. A mirror plane at a distance D is used as a focus area where a focus error signal is detected and is maintained during a subsequent data byte section.
When a DRAW disk of, for example 5 inches in which a servo byte thus described is stored, is caused to rotate at a rate of 1800 rpm, the edge produced in the RF signal due to the clock pit will occur at a frequency of 41.28 kHz.
FIG. 4 shows an example of a clock producing circuit for producing a clock signal to enable the reproduction of data which have been stored after the servo byte on such DRAW disks. In FIG. 4, the RF signal obtained from a disk (not shown) by means of a pickup 1 is amplified by a head amplifier 2 and then is supplied to a differentiation edge detection circuit 3. The differentiation edge detection circuit 3 is arranged to output edge pulses which are a train of pluses corresponding to the respective detected signal-edge which is obtained by differentiating the RF signal. The edge pulses a which are output from the circuit 3, are supplied to a synchronism detection circuit 4 and to one of the input terminals of an AND gate 5. The synchronism detection circuit 4 is supplied with a reproducing clock signal from a PLL (Phase Locked Loop) circuit 6. The synchronism detection circuit 4 measures the period between two successive pulses in the train of edge pulses a by counting the reproducing clock signal pulses and then outputs a sync-signal detection signal b when the measured count of the reproducing clock signal pulses equals a predetermined value. The sync-signal detection signal b is supplied to a gate pulse generating circuit 7. The gate pulse generating circuit 7 is arranged to generate a clock gate pulse having a predetermined duration in a predetermined time after the sync-signal detection signal b has been output, on the basis of the reproducing clock signal pulses from the PLL circuit 7. The clock gate pulse from the gate pulse generating circuit 7 is supplied to the other input terminal of the AND gate 5.
The output of the AND gate 5 is supplied to a phase comparator circuit 8 of the PLL circuit 6. The phase comparator circuit 8 performs phase comparison between the output of the AND gate 5 and the output of a divider circuit 9 to supply the result of the phase comparison to a low pass filter 10 (referred to as LPF hereafter). The signal filtered out by the LPF 10 is supplied as a control voltage to a voltage controlled oscillator 11 (referred to as VCO hereafter). A reproducing clock signal (for instance, 11.1456 MHz having a phase in accordance with the control voltage is output from the VCO 11. The reproducing clock signal e is divided by 270 by the divider circuit 9, and is then supplied as a signal of 41.28 kHz to the phase comparator circuit 8.
In the arrangement thus described, when the light spot of the pickup 1 traces the servo byte, the level of the RF signal decreases at a pit location, thus the edge pulses as shown in FIG. 5(A) in accordance with the location of pits are output from the differentiation edge detection circuit 3. When the time between successive edge pulses a becomes equal to the time corresponding to the distance D, the sync-signal detection signal b is output. The gate pulse generating circuit 7 generates a gate pulse c as shown in FIG. 5(B) for gating a clock edge pulse generated in accordance with the clock pit, on the basis of the sync-signal detection signal b. Supplying the edge pulses a and the gate pulse c to the AND gate 5 causes the AND gate 5 to output only the clock edge pulse d corresponding to a clock pit as shown in FIG. 5(c), which is supplied to the phase comparator circuit 8 of the PLL circuit 6. As a result, the PLL circuit 6 generates the reproducing clock e of 11.1456 MHz in synchronism with the clock edge pulse d.
If a 5 inch DRAW disk is rotated at 1800 rpm, the frequency of the clock pit (clock edge pulse) will be 41.28 KHz. If the pulse length of the clock edge pulses is a half of the clock signal (approximately 45 ns), the energy distribution of the clock edge pulse will be as shown in FIG. 6 where the spectra appear intermittently at a spacing equal to the sampling frequency of 41.28 KHz, centered about the clock frequency of 11.1456 MHz. The spectra will be as shown in FIG. 7 when the pulse length of the clock edge pulse is varied. In a prior art clock producing circuit shown in FIG. 4, since the phase comparator circuit 8 compares the input signals of identical frequencies, there is no possibility that the PLL is mistakenly locked to 11.456 MHz .+-.4l.28N KHz (N is an integer). However, there is a shortcoming in that due to the precision of the phase comparator circuit 8 equaling 1/270, jitter of the clock signal may be increased. Another problem is that stable detection of the syncsignal is not effected initially, thus requiring more time before the PLL is locked, since detection of the syncsignal is effected by the reproducing clock signal which is output from the PLL circuit 6 and also the sync-signal which produces a gate pulse to select the clock edge pulse d to be supplied to the PLL circuit 6.